Field of the Invention
The present invention relates to an array substrate including a non-linear element and also relates to a liquid crystal display including the array substrate.
Description of the Background Art
Common examples of liquid crystal display modes include the twisted nematic (TN) mode and the transverse electric field mode for achieving a wide viewing angle and a high contrast, such as the in-plane switching mode and the fringe field switching (FFS) mode. Liquid crystal displays employing the IPS mode perform display by applying a transverse electric field to liquid crystals sandwiched between opposed substrates. In such a liquid crystal display, a pixel electrode and a common electrode to which the transverse electric field is applied are located on the same layer. Thus, the liquid crystal display fails to drive liquid crystal molecules located above the pixel electrode sufficiently and has a low transmittance accordingly. Meanwhile, a liquid crystal display employing the FFS mode is capable of driving liquid crystal molecules located above the pixel electrode by using a fringe electric filed, and thus, has a transmittance higher than that of the liquid crystal display employing the IPS mode.
In such a common matrix liquid crystal display, display materials including liquid crystals are sandwiched between two substrates opposed to each other such that a voltage can be selectively applied to the display materials. At least one of the two substrates is referred to as a matrix array substrate (hereinafter simply referred to as an “array substrate”). On the array substrate, switching elements such as thin film transistors, source wires, and gate wires are arranged in array. The source and gate wires provide signals to the switching elements.
In general, the array substrate is an insulation substrate made of, for example, glass. Thus, a short circuit arising from electrical breakdown or the like is more likely to occur between the source wire and the gate wire due to static electricity created in the manufacturing process. A common workaround to this problem is to dispose a low-resistance wire, which is referred to as a short ring wire, on the periphery of the array substrate. The short ring wire is connected to the source wire through a bidirectional diode (a protection circuit) and is also connected to the gate wire through another bidirectional diode. In this configuration, the source wire and the gate wire are at the same potential (see, for example, Japanese Patent No. 5080172 and Japanese Patent Application Laid-Open No. 2010-092036).
Each diode included in the protection circuit is required to have a reasonably high resistance. The conventional diode made of amorphous silicon with a channel length of about 5 to 10 μm and a channel width of about 5 to 10 μm offers an acceptable diode resistance because an amorphous silicon film included in the diode has a high resistance.
In order to provide a high definition display or a display with an on-board driving circuit, considerable work has been done on the development of thin film transistors (TFT's) including oxide semiconductors, as alternatives to conventional TFTs made of amorphous silicon. Such an oxide semiconductor has a mobility that is two orders of magnitude greater than that of an amorphous silicon film and also has a higher carrier concentration, so that the diode resistance of the oxide semiconductor is two to three orders of magnitude lower than that of the amorphous silicon film. The diode with increased resistance inevitably has a longer channel length, which may be as long as several tens of micrometers. The diode element increases in size due to such an increase in channel length, and a frame region of the array substrate expands accordingly, making it difficult to obtain an array substrate with a narrow frame. To solve the above-mentioned problems, a structure has been disclosed which includes a source electrode disposed on an oxide semiconductor layer, a drain electrode disposed below the oxide semiconductor layer, and a gate electrode disposed so as to cover a sidewall of the oxide semiconductor layer. In this structure, the gate electrode is connected to the source electrode or the drain electrode, and the sidewall of the oxide semiconductor functions as a channel (see, for example, Japanese Patent Application Laid-Open No. 2015-092601).
While being processed, the oxide semiconductor layer included in the structure disclosed in Japanese Patent Application Laid-Open No. 2015-092601 is susceptible to etching damage, with a defect in the surface of the sidewall of the oxide semiconductor layer. A leakage current is likely to occur in the defect. In this structure, the channel length is short, so that the leakage current is more likely to occur, making it difficult to control resistance.